1. Field of the Invention
The present invention relates to a Gigabit Ethernet communication system, and apparatuses for transmission and reception of transmission signals of a plurality of channels of Gigabit Ethernet, as well as a multiplexing transmission method therefor.
2. Description of Relevant Art
Gigabit Ethernet (a registered trademark of Xerox Co.) is specified in IEEE Std802.3, 1998, of the IEEE (Institute of Electric and Electronic Engineer) Standards. Conventionally, in cases of transmission data of Gigabit Ethernet to be electrically multiplexed for transmission and reception, there has been employed a method called “frame multiplexing”.
As shown in FIG. 1, two apparatuses 01 and 02 for transmission data of Gigabit Ethernet electrically multiplexed to be thereby transmitted and received are respectively constituted with a Gigabit Ethernet multiplexer 20 and a Gigabit Ethernet demultiplexer 30. The apparatuses 01 and 02 are transmitter/receivers identical in constitution. The two transmitter/receivers are connected by a pair of optical fiber cables as transmission means 03 and 04, for bi-directional transmission. Continuous 10 bits of transmission data constitute a 10-bit data, and a plurality of continuous 10-bit data constitute a unit called “frame”. In Gigabit Ethernet, transmission data are transmitted and received in the unit of frame. In the case of Gigabit Ethernet, the frame has a length of continued data between 64 bytes to 1518 bytes.
In the multiplexer 20 of a multiplexed signal transmitter/receiver to be used for a multiplexing transmission of 2-channel Gigabit Ethernet, as shown in FIG. 2, arriving frames at respective channels of Gigabit Ethernet are once stored in transmission memories (buffer memories) 22 and 23 of the channels, and the stored frames are sent to a multiplexing transmission processor 21, where they are multiplexed with information of channel identification numbers added to the frames, and the multiplexed frames are transmitted to a multiplexed signal transmission line 04. The transmission memories 22 and 23 respectively needs a capacity of at least 12144 (=1518×8) bits. In the case of 2 channels, the transmission memories are required to have a total capacity of at least 24288 (=12144×2) bits. In a case of n channels, a total capacity of transmission memories should be at least 12144×n bits.
On the other hand, in the demultiplexer 30 of a multiplexed signal transmitter/receiver to be used for a multiplexing transmission of 2-channel Gigabit Ethernet, as shown in FIG. 3, there are frames multiplexed by a multiplexing transmission processor of a Gigabit Ethernet multiplexed signal transmitter/receiver of the same constitution as described, with channel identification numbers added, and received from the transmission means 03 at a demultiplexing processor 31, where the frames with the channel identification numbers are deprived of information of the identification numbers, to be transferred to corresponding channels 1 and 2 of Gigabit Ethernet.
Like this, conventionally, transmission data of Gigabit Ethernet have been electrically multiplexed to be transmitted and received by a Gigabit Ethernet multiplexed signal transmitter/receiver using the method called “frame multiplexing”.
However, the multiplexed signal transmitter/receiver using the conventional technique has the following problems.
At the multiplexer of the multiplexed signal transmitter/receiver, where arriving frames at respective channels of Gigabit Ethernet are once stored the transmission memories of the channels before transfer of the stored frames to the multiplexing transmission processor, there is needed every channel a great buffer memory for storing a frame.
Moreover, at the multiplexer of the multiplexed signal transmitter/receiver, sent frames from transmission memories to a multiplexing transmission processor are needed to be once received by the multiplexing transmission processor for processing the frames by adding identification numbers of channels, and further at the demultiplexer of the multiplexed signal transmitter/receiver, when a demultiplexing processor has received frames with added channel identification numbers, there are needed complicated processes such as for the demultiplexing processor to take information of identification numbers out of the frames having the added channel identification numbers. Yet further, for a match between channel identification numbers to be ensured at both the multiplexer and demultiplexer, there are needed additional processes such as for re-calculation of a frame check sequence (by error detection code).
In another conventional art as explained “A System for Native Ethernet Optical Transport at 10 Gb/s submitted to 2000 Conference on Optical Fiber Communications”, although link performance is qualified with a 231−1 pseudo-random bit sequence at 10.000 Gb/s, the multiplexed data stream is a bit-wise multiplexed 8 b/10 b stream. The 8 b/10 b-multiplexed stream has considerably reduced low-frequency content due to restrictions of 8 b/10 b code, which specify no more than 4 sequential identical bits.
Multiplexer interface boards provide an interface to discrete Gigabit Ethernet signals on both the transmit and receive paths. Two such boards are stacked to provide full connectivity for 8 Gigabit Ethernet sources. Clock synchronization and bit-stream identification are the major multiplexer interface board functions. These functions are accomplished by taking advantage of the features of the Gigabit Ethernet standard, specifically the start and end of frame delimiters, and required idle characters between packets.
Clock synchronization is performed through the use of a first-in-first-out buffer. After reception, incoming Gigabit Ethernet packets are deserialized with a commercial serializer/deserializer that also performs clock recovery and word alignment of the incoming packets. The word-parallel data is clocked out in a 20-bit bus at 62.5 MHz. A complex programmable logic device detects the start and end of a given packet. The logic device places valid packets into the buffer. Another logic device monitoring the 10-bit-wide buffer output reads this data at a synchronous system clock rate of 125 MHz. When packets are not available, link specific idle characters are generated by this logic device. Data is then serialized for multiplexing with another commercial serializer/deserializer.
However, in one-bit-wise multiplexing, there is a great chance for greater run length. In case of 8 channel multiplexing, run length (sequential identical bits) can be as long as 32 bits as the longest run length of a single channel is 4 bits as specified by 8 b/10 b code. The greater run length, such as 32 bits, can cause greater chance of receive error as there is no signal level change for the 32 bits time. In the document referred above, some frame losses caused by receive error are reported and these losses may have been caused by the longer run length of the multiplexed signal.
However, a great run length provides a great transmission error. An idle code of transmission signal needs a replacement with a special code for channel identification. This replacement fails to hold a running disparity of 10-bit code in each channel.